A wireless device such as a cellular telephone typically includes various components that communicate status, control and data information to each other. For example, a cellular telephone typically includes a transceiver that is adapted to transmit and receive at radio frequencies (RF). Cellular telephones further include a baseband processor that operates at baseband frequencies. Typically, information used to control the transceiver is provided from the baseband processor via digital signals on multiple pins, such as general purpose input/output (GPIO) pins. Additionally, baseband processors typically transmit radio data (e.g., voice information) to the transceiver via analog signals. Because there is a significant amount of information that is needed to be transferred, numerous such pins are needed, raising complexity, cost and consuming additional chip real estate.
For various reasons, digital interface communication protocols have been discussed in the communications industry, particularly with respect to cellular phones. One such effort has resulted in the DigRF Baseband/RF Digital Interface Specification currently available on the Internet at the following URL—http://www.ttpcom.com/digrf. This specification defines certain logical, electrical and timing characteristics for a digital interface between an RF integrated circuit (RFIC) such as a transceiver and a baseband processor.
For many mobile systems, including those compliant with the DigRF standard, exchange and storage of power control ramping information represents a major problem in terms of software/firmware complexity and/or hardware cost. Many systems provide ramp profile information from a baseband processor to the RFIC. However, to digitally transmit this data, complex operations are needed for conveying the transmit power control ramp information, as well as constructing appropriate power control ramp profiles. This complexity, from a baseband processor perspective, is both arduous in terms of software (e.g., programming) and RFIC interface traffic. One solution is to pre-store ramps in memory of the RFIC. This memory can be loaded once or infrequently by the baseband processor and accessed, e.g., on a transmit burst-by-burst basis by the RFIC. However this solution has some key disadvantages, as it may require high voltage or nonvolatile memory on the RFIC which is physically large (to achieve low leakage current). Furthermore, a large amount of memory may be needed if all possible ramping profiles are to be pre-stored.